#ifndef __CC1100_ARCH_H__
#define __CC1100_ARCH_H__
#include<cfg/SysConfig.h>

#define GDO_INIT() do \
{ \
  P1SEL &= ~(GDO0_PIN | GDO2_PIN); \
  P1DIR &= ~(GDO0_PIN | GDO2_PIN); \
  P1IE  &= ~(GDO0_PIN | GDO2_PIN); \
} while (0)

/**
 * \brief Enable Interrupt for GDO0 pin
 **/
#define GDO0_INT_ENABLE() MASK_1(EIMSK, CC_GDO0_BINT)

/**
 * \brief Enable Interrupt for GDO2 pin
 **/
#define GDO2_INT_ENABLE() MASK_1(EIMSK, CC_GDO2_BINT)

/**
 * \brief Disable Interrupt for GDO0 pin
 **/
#define GDO0_INT_DISABLE() UNMASK_1(EIMSK, CC_GDO0_BINT)

/**
 * \brief Disable Interrupt for GDO2 pin
 **/
#define GDO2_INT_DISABLE() UNMASK_1(EIMSK, CC_GDO2_BINT)

/**
 * \brief Clear interrupt flag for GDO0 pin
 **/
#define GDO0_INT_CLEAR() MASK_1(EIFR, CC_GDO0_BINT)
/**
 * \brief Clear interrupt flag for GDO2 pin
 **/
#define GDO2_INT_CLEAR() MASK_1(EIFR, CC_GDO2_BINT)


/**
 * \brief Set edge interrupt for GDO0 pin
 **/
#if (CC_GDO0_BINT>3)
#define GDO0_INT_SET_RISING()    MASK(EICRB, 0x3/*0b11*/<<((CC_GDO0_BINT-4)<<1))/* atomic operation */
#define GDO0_INT_SET_FALLING()   MASK(EICRB, 0x2/*0b10*/<<((CC_GDO0_BINT-4)<<1))/* atomic operation */
#else
#define GDO0_INT_SET_RISING()    MASK(EICRA, 0x3/*0b11*/<<(CC_GDO0_BINT<<1))
#define GDO0_INT_SET_FALLING()   MASK(EICRA, 0x2/*0b10*/<<(CC_GDO0_BINT<<1))
#endif

/**
 * \brief Set edge interrupt for GDO2 pin
 **/
#if (CC_GDO2_BINT>3)
#define GDO2_INT_SET_RISING()    MASK(EICRB, 0x3/*0b11*/<<((CC_GDO2_BINT-4)<<1))/* atomic operation */
#define GDO2_INT_SET_FALLING()   MASK(EICRB, 0x2/*0b10*/<<((CC_GDO2_BINT-4)<<1))/* atomic operation */
#else
#define GDO2_INT_SET_RISING()    MASK(EICRA, 0x3/*0b11*/<<(CC_GDO2_BINT<<1))
#define GDO2_INT_SET_FALLING()   MASK(EICRA, 0x2/*0b10*/<<(CC_GDO2_BINT<<1))
#endif

/**
 * \brief Read GDO0 pin value
 **/
#define GDO0_READ() PM_PINH(CC_GDO0)//CHECK_PORT(CC_GDO0)
/**
 * \brief Read GDO2 pin value
 **/
#define GDO2_READ() PM_PINH(CC_GDO2)



#define MRFI_GDO0_INT_FLAG_IS_SET()       CHECK(EIFR, CC_GDO0_BINT)
#define MRFI_GDO0_INT_FLAG_IS_ENABLED()   CHECK(EIMSK, CC_GDO0_BINT)

#define MRFI_GDO0_PIN_IS_HIGH()           PIN_H( CC_GDO0 )


#define MRFI_SPI_SO_IS_HIGH()   PIN_H(CC_MISO)
#define MRFI_SPI_CSN_IS_HIGH()  PIN_H(CC_SS)

#define CC1100_DRIVE_CSN_LOW()   CLR( CC_SS )
#define CC1100_DRIVE_CSN_HIGH()  SET( CC_SS )

#define SPI_ENABLE()             CLR( CC_SS )
#define SPI_DISABLE()            SET( CC_SS )







void    cc1100_arch_init(void);

uint8_t spi1_write_single(uint8_t byte);
uint8_t spi1_read_single(void);

uint8_t cc1100_read_reg   (uint8_t addr);
uint8_t cc1100_read_status(uint8_t addr);

void    cc1100_write_reg  (uint8_t addr, uint8_t value);
uint8_t cc1100_strobe_cmd (uint8_t cmd);

void    cc1100_fifo_put(uint8_t* hdrbuf, uint8_t* buffer, uint16_t applength);
void    cc1100_fifo_get(uint8_t* buffer, uint16_t length);



#endif
